Along with the development of smaller, multifunctional, high-performance electronic devices in recent years, demands have emerged for advanced high-density packaging of semiconductor parts. An important technical challenge in the art is finding a way to realize a downsized (thinned) semiconductor package having improved heat dissipation capacity. Examples of such semiconductor package types include the CSP (Chip Size Package), the BGA (Ball Grid Array) package, the LGA (Land Grid Array) package, the MCP (Multi Chip Package), and the SiP (System in Package).
Regarding semiconductor package downsizing (thinning), there is a leadless-type semiconductor package available on the market that is obtained by partially exposing electrode terminals on the package bottom or side faces without sealing the electrode terminals inside a resin so as not to expose lead wires.
In addition, regarding the heat dissipation capacity of a semiconductor package, there is a semiconductor package available on the market that has a structure in which a die pad (heat dissipating pad) that functions as a radiator plate is partially exposed and is not sealed inside a resin or a structure in which a built-in radiator plate prepared as a separate body is provided.
A semiconductor package having a structure in which a heat dissipating pad is entirely or partially exposed outside a sealant resin body is relatively superior in terms of heat dissipation capacity to a semiconductor package having a built-in radiator plate prepared as a separate body. Therefore, such semiconductor package is preferably used in a case in which a semiconductor element that generates a large amount of heat is installed.
Each of FIGS. 7 and 8 shows an example of a semiconductor device, in which the aforementioned leadless-type semiconductor package is mounted on a substrate, such semiconductor package having a structure in which a heat dissipating pad is partially or entirely exposed. In addition, each example shows a semiconductor device in which a heat dissipating pad is entirely exposed outside a sealant resin body; that is to say, a heat dissipating pad is completely exposed on one side of the sealant resin body facing the substrate. FIG. 7 shows a longitudinal sectional view of such device. FIG. 8 shows a VIII-VIII fragmentary view of FIG. 7.
In FIGS. 7 and 8, a semiconductor element “a” is mounted on a heat dissipating pad “c” via joining using a die-bonding material “b” such as an electrically conductive adhesive so as to achieve electrical connection to electrodes d1 and d2 (outermost circumference side: d1) with leads “e.” Further, the heat dissipating pad “c” and the electrodes “d1 and d2” are disposed on the lower face of a sealant resin body “f” that seals the semiconductor element “a” (provided that an electrode or a heat dissipating pad may be partially embedded in a sealant resin body). Thus a semiconductor package “P” is formed. The heat dissipating pad “c” and the electrodes “d1 and d2” of the semiconductor package “P” are joined to a substrate “g” via a solder layer “h,” and thus a semiconductor device “H” is formed.
As an aside, in a case of a conventional semiconductor device “H” shown in FIG. 7 or 8, a package “P” and a substrate “g” are heated during reflow soldering in a step of joining a heat dissipating pad “c” and electrodes “d1 and d2” to the substrate “g” via reflow soldering. This results in vaporization and expansion of moisture absorbed in the package “P” during the period from assembly to mounting. This information is publicly known.
In general, the rigidity of a substrate “g” is relatively higher than that of a semiconductor package “P.” In addition, the thermal expansion coefficient of the substrate “g” is relatively lower than that of the semiconductor package “P” (and therefore the semiconductor package “P” is unlikely to experience thermal deformation). This information is publicly known.
Therefore, upon reflow soldering described above, the substrate “g” has a high degree of rigidity and a low thermal expansion amount, while on the other hand, the semiconductor package “P” has a relatively low degree of rigidity and a relatively high thermal expansion amount. Therefore, for example, a deformation mode of the semiconductor package “P” is observed in which the area of the semiconductor element “a” projects toward the substrate “g,” and portions in the vicinity of electrodes “d1 and d2” located at a distance from the area of the semiconductor element “a” roll back against the substrate “g.” For example, as in the example shown in FIG. 7, when a semiconductor package “P” has a structure in which a semiconductor element “a” is disposed at the center position and electrodes “d1 and d2” are disposed on the outer circumference side of the semiconductor element “a,” a deformation mode of the semiconductor package “P” is observed in which the edge portions including the electrodes “d1 and d2” of the semiconductor package “P” rolls back against the substrate “g” (indicated with a single-dot chain line in FIG. 7).
As a result, when the electrodes “d1 and d2” disposed on the outer circumference side of the semiconductor package “P” are joined to the substrate “g,” shear force or tensile force “Q” is applied to a solder layer “h,” which is a constituent member of the semiconductor package “P” and corresponds to a strucuturally weak portion of the semiconductor package “P,” easily causing detachment or crack formation. This has been probelamtic. Also, detachment of the semiconductor element “a” from the heat dissipating pad “c” due to excessive deformation of the semiconductor package “P,” detachment of the heat dissipating pad “c” from the sealant resin body “f,” and crack formation in the sealant resin body “f” have been problematic. It is an urgent task in the art to solve such problems.
Here, disclosed conventional techniques are intended to prevent warpage of a semiconductor package and destruction of constituent members of a semiconductor device caused by warpage described above. For such purpose, Patent Document 1 discloses a semiconductor package in which a radiator plate is provided at the center of the thickness of a semiconductor device, and a semiconductor element, a mold resin, and an interposer substrate are provided below and above the radiator plate, resulting in line-symmetric arrangement along the line passing through the center of the thickness.
In addition, the thermal expansion coefficient of the semiconductor package is obtained using the two interposer substrates that constitute the semiconductor package. Eventually, the thermal expansion coefficient of a mounted substrate upon which the semiconductor package is joined via reflow soldering is made approximately equal to that of the semiconductor package so as to reduce differences in the amount of displacement between the semiconductor package and the mounted substrate.
However, it can be easily predicted that it will be difficult to manufacture a semiconductor package with a line-symmetric configuration along the line passing through the center of the thickness, and manufacturing of such semiconductor package will result in higher costs. In addition, from a practical standpoint, it must be said that the general versatility of such vertically or horizontally symmetric semiconductor package is low. Therefore, it is difficult to say that the use of such semiconductor package is a practical and effective way to solve the above problems in the art.
Patent Document 1: JP Patent Publication (Kokai) No. 2006-93679 A